Digital twins drive chip development
Siemens and Saicec accelerate SDV chip validation
The collaboration enables verification across multiple abstraction layers in one environment.
Siemens
Siemens and Saicec plan to speed up the validation of automotive chips by applying advanced digital-twin technology. Their joint approach targets faster certification cycles and more reliable system-level testing.
As automotive electronics become more central to vehicle
performance, the pressure to validate chips earlier and more reliably continues
to grow. The German technology conglomerate Siemens notes that development
teams often lack system-wide insight until late in the process, creating blind
spots that can trigger delays and costly redesigns. To close this gap, the
Germans and the Chinese chip-design specialist Saicec
(Shanghai Automotive IC Engineering Center) are shifting validation into a
fully virtual, system-to-chip environment.
Digital twins at the start of development
Their collaboration centres on Siemens’ PAVE360 platform, a
virtual engineering environment capable of creating detailed digital twins of
entire vehicle electronics. Combined with the Innexis software framework, the
platform allows ADAS, infotainment and broader system
architectures to be modelled long before physical hardware exists.
These digital twins can be connected to reference vehicles,
enabling engineers to observe system behaviour from the earliest stages of
development. Instead of discovering integration issues only when hardware
prototypes arrive, teams gain an immediate view of interactions across the full
stack — from high-level systems down to chip-level logic.
Saicec has already begun constructing high-fidelity virtual
architectures using the PAVE360 toolchain. This system-to-chip approach enables
verification across multiple abstraction layers in one environment, reducing
the likelihood of late-phase corrections and supporting more predictable
development cycles.
A scalable framework
Digital twins act as an early testbed where engineers can
explore edge cases, optimise configurations and validate functionality without
waiting for physical components. This approach helps align performance, safety
and architectural decisions long before production hardware is finalised.
According to Saicec CEO David He, Siemens’ system-to-chip
digital-twin capabilities enable his teams to shorten development timelines,
strengthen functional safety and lay a more robust foundation for intelligent
mobility architectures.
Mike Ellow, CEO of Siemens EDA within Siemens Digital
Industries Software, similarly highlighted that PAVE360 offers the digital-twin
environment Saicec requires for its next-generation validation workflows. He
also noted that the platform’s scalable, multi-fidelity structure is designed
to support consistent verification throughout the entire vehicle-development
process.
