Interview with Dr Ali Safiei, Black Semiconductor
“Sensor-to-core connectivity faces a different scaling challenge”
Before joining Black Semiconductor, Dr Ali Safiei was Senior Vice President at Volkswagen’s software subsidiary Cariad.
Dr. Ali Safiei
As vehicle compute grows, data movement is becoming a core bottleneck for future E/E architectures. Black Semiconductor’s Dr Ali Safiei explains how optical PCIe and graphene photonics could reshape automotive HPC.
Future vehicle architectures are no longer limited by compute performance alone. As sensors, accelerators, memory systems and centralised HPC units exchange growing amounts of data, the efficiency of data movement is becoming a decisive design factor.
Dr Ali Safiei, Senior Principal Product Management – Automotive, Robotics & Edge at Black Semiconductor, works on optical interconnect chipsets, chiplet-photonic compute and graphene-enabled technologies. At the Automotive Computing Conference Germany in Munich, he will give a keynote on “Integrated Graphene Photonics as Optical PCIe for Zonal Backbone and Optical Interconnect for Chiplets”.
Ahead of the event, we spoke with Dr Safiei about copper limits, optical PCIe, chiplet qualification and the point at which data movement becomes more critical than compute itself.
Is data movement, not compute, the next fundamental bottleneck in automotive HPC, and which metric will reveal that crossover first?
Yes, I believe data movement is becoming one of the fundamental constraints of automotive high-performance computing. Physical AI systems increasingly depend not only on processing large amounts of data, but on moving that data efficiently: from high-bandwidth sensors into centralised compute, and between processors, memory and accelerators within the compute system. I would therefore not define the crossover by a single bandwidth number. A more meaningful indicator is the energy and system cost of moving a bit relative to processing it. Once interconnect power, SerDes overhead, wiring, EMC measures and packaging complexity consume a disproportionate part of the overall system budget, we have a data-movement problem rather than simply a compute problem. This is why metrics such as bandwidth per watt and bandwidth per physical interface will become increasingly important alongside traditional compute metrics such as TOPS.
At what architecture scale does copper become economically or physically unsustainable for zonal backbones and chiplet interconnects?
There is no single bandwidth or distance at which copper suddenly becomes unsustainable. We need to distinguish between different architectural domains. At chiplet level, electrical die-to-die connectivity remains extremely efficient over very short distances. As chiplet systems scale beyond a single package, however, the combination of bandwidth density, energy per bit, reach and packaging complexity increasingly makes optical I/O attractive. The opportunity is therefore not necessarily to replace short-reach electrical die-to-die interfaces, but to complement them when scaling beyond package boundaries. At vehicle level, sensor-to-core connectivity faces a different scaling challenge. Cameras, radar, lidar and other high-bandwidth sensors need to transport increasing amounts of data over much longer distances under strict EMC, weight, power and wiring constraints. In both cases, the question is therefore not simply “How far can copper go?”, but rather “At what point does maintaining the electrical link become the dominant system constraint?”
As automotive compute performance rises, at what point does electrical data movement between processors, memory and accelerators become a more serious bottleneck than compute itself?
We are already seeing the beginning of this transition in AI computing generally. Increasing accelerator performance only creates value if data can be delivered to the compute engines efficiently enough. In automotive, the challenge exists at two levels: inside the compute system, between processors, memory and accelerators, and across the vehicle, between sensors, zonal controllers and centralised compute. The crossover will therefore not occur at one specific TOPS number. It emerges when scaling compute requires a disproportionate increase in memory bandwidth, interconnect power, I/O bandwidth and physical infrastructure. This is why future automotive HPC architectures should not optimise compute, memory and networking independently. They increasingly need to be designed as one integrated system, with data movement treated as a first-class architectural parameter.
Does optical interconnect need to beat copper on every metric, or is there one decisive threshold in bandwidth density, power, EMC, cost or qualification that triggers adoption?
I do not believe optics needs to beat copper on every individual metric. The decisive point will be the overall system-level economics. Bandwidth density, power and EMC can create the technical need for optics, but cost, integration and qualification will determine whether it can scale into high-volume automotive applications. This is particularly important for sensor-to-core connectivity. Simply replacing an electrical cable with a discrete optical transceiver and fibre does not fundamentally solve the system-cost problem. The larger opportunity comes when photonic functionality can be integrated directly with the electronic IC. This is the approach we are pursuing with integrated graphene photonics at Black Semiconductor. By enabling monolithic integration of photonic functionality with an EIC, the objective is to reduce the additional component, interface and packaging overhead traditionally associated with optical connectivity. That has the potential to fundamentally change the system-cost equation and make optical connectivity relevant not only for premium point solutions, but for scalable sensor-to-core architectures.
Chiplet architectures promise greater flexibility and reuse. How do they change the automotive qualification problem when compute, I/O, accelerators and photonics may come from different suppliers and process technologies?
Chiplets change qualification from primarily a component-level problem into a system-in-package problem. In a heterogeneous chiplet architecture, the final product may combine compute dies, I/O dies, accelerators, memory interfaces, photonics and advanced packaging from different processes and potentially different suppliers. The key challenge is that reliability interactions do not stop at the die boundary. Thermal behaviour, mechanical stress, interconnect reliability, package interfaces and failure propagation become system-level concerns. Automotive qualification therefore requires clear ownership of the overall mission profile, reliability targets and qualification strategy. Individually qualified components do not automatically result in a qualified system. I believe this will become one of the fundamental challenges of heterogeneous integration in automotive: the industry needs qualification methodologies and ownership models that reflect the behaviour of the complete product, not just its individual dies.
Based on your experience on both the OEM software-platform side and the semiconductor side, where is the largest mismatch between what vehicle software teams want from future HPC hardware and what semiconductor roadmaps are currently optimising for?
The largest mismatch is that software organisations increasingly want hardware to be optimised around their specific workloads and system architecture, while semiconductor roadmaps traditionally need scale, standardisation and long development cycles. I believe much stronger system hardware/software co-design will be required to close this gap. Future vehicle compute cannot be developed by defining the semiconductor first and mapping the software onto it afterwards. Workloads, compute, memory, accelerators and data movement need to be architected together much earlier. However, this creates another challenge: the more closely hardware is optimised together with the software stack, the more we move towards semi-custom solutions. Developing a completely new monolithic SoC for every OEM, vehicle platform or workload is neither economically scalable nor compatible with automotive development cycles.
This is where chiplet architectures can create a significant opportunity. Instead of customising the entire SoC, we can potentially combine reusable standard building blocks — compute, memory, I/O or connectivity — with differentiated or application-specific chiplets. This allows a much higher degree of system optimisation without requiring a completely new monolithic semiconductor for every application. In my view, this could become an important source of differentiation: standardisation at the building-block level, combined with customisation at the system level. The interconnect architecture then becomes critical because it determines how efficiently and flexibly these building blocks can be combined.
If optical PCIe succeeds in automotive, which part of the E/E architecture changes first: wiring, zonal topology, packaging, thermal design or the supplier structure?
The first visible change may be wiring, but I believe the much more fundamental change will happen at semiconductor and system level. Optical PCIe becomes particularly interesting if we do not treat optics as an additional external component, but integrate the optical interface directly into the electronics. Conventional approaches often require separate photonic dies, additional packaging and optical/electrical interfaces. This adds cost, complexity and additional reliability interfaces. This is where Black Semiconductor’s integrated approach can fundamentally change the equation. With integrated graphene photonics, the photonic functionality can be monolithically integrated with the electronic IC. In principle, this allows optical PCIe connectivity to be integrated much closer to, and potentially directly into, sensors, processors, accelerators or other electronic devices. The consequence is important: instead of adding an expensive optical transceiver to an existing electrical architecture, optical connectivity becomes part of the semiconductor itself. This has the potential to significantly reduce component and packaging overhead while eliminating interfaces that otherwise have to be assembled and qualified separately.
For automotive, that could make optical PCIe relevant far beyond a premium HPC-to-HPC link. It opens the possibility of a scalable optical fabric from sensor-to-core and potentially core-to-core, while maintaining the PCIe ecosystem at the logical interface level. In the longer term, this could change not only wiring, but also zonal topology, packaging and the supplier structure, because the boundary between compute, connectivity and optical networking starts to disappear. One aspect that deserves more attention is that the automotive industry should not treat optical connectivity simply as a faster replacement for copper. If we replace an electrical cable with an optical cable while keeping exactly the same E/E architecture, we capture only part of the potential value. The larger opportunity is architectural: reconsidering how sensing, compute and data movement are designed together in future Physical AI systems.
